{"title":"Model Parameter Extraction for the High Voltage SOI-Process using BSIMSOI3 Model and ICCAP","authors":"J. Pieczynski, T. Gneiting","doi":"10.1109/MIXDES.2007.4286126","DOIUrl":null,"url":null,"abstract":"This paper presents a procedure for electrical parameter extraction of high voltage SOI MOS transistors. Several types of NMOS and PMOS fully depleted SOI devices were measured and modelled in a voltage ranging up to 30V. The standard Berkeley BSIMSOI3 model with ICCAP software was applied as a basis for modelling work. In order to increase the maximum operation voltage of the MOSFETs, a number of devices were designed and fabricated with additional drain extension structures. However, this resulted in problematic parasitic effects, such as back gate control of the drain extension and drain current quasi-saturation. In order to account for these effects in the modelling procedure, special sub-circuits containing transistors, resistors and voltage sources were implemented.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"54 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MIXDES.2007.4286126","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper presents a procedure for electrical parameter extraction of high voltage SOI MOS transistors. Several types of NMOS and PMOS fully depleted SOI devices were measured and modelled in a voltage ranging up to 30V. The standard Berkeley BSIMSOI3 model with ICCAP software was applied as a basis for modelling work. In order to increase the maximum operation voltage of the MOSFETs, a number of devices were designed and fabricated with additional drain extension structures. However, this resulted in problematic parasitic effects, such as back gate control of the drain extension and drain current quasi-saturation. In order to account for these effects in the modelling procedure, special sub-circuits containing transistors, resistors and voltage sources were implemented.