Optimization of thermal resistance in quasi monolithic integration technology (QMIT) structure

Abstract

Quasi-monolithic integration technology (QMIT) is a new alternative to monolithic circuit fabrication for microwave and millimeter wave integrated circuits. Static thermal analysis of the standard QMIT structure has already been performed and the effects of different factors and parameters such as epoxy thermal conductivity, distance between active device and Si substrate (W), front side substrate metallization and heat spreader on the back side have been described (Joodaki et al, 2000). In the first structure (or standard structure) of QMIT, the holes in which the active devices are placed have been created by using conventional wet etching of silicon in KOH. It is well known that by using dry etching, the hole dimensions on the front side of the Si-wafer are more uniform, accurate and reproducible. There are two other possible structures, by using full dry etching, and through a combination of wet etching and dry etching. In this paper, a 2D finite element (FE) static heat transfer simulation has been used to find the best structure among these three structures and optimise its geometry and all its physical properties for lower thermal resistance, which makes it possible to use QMIT for high power microwave circuit applications. The results show that a combination of dry etching and wet etching gives a lower thermal resistance than the other two and with backside plating of 275 /spl mu/m gold as a heat spreader, epoxy thermal conductivity of 4 W/m.K and W of 5 /spl mu/m, a thermal resistance of less than 10/spl deg/C/W is possible.