INTEGRATING CROSSCHECK TECHNOLOGY INTO THE RAYTHEON TEST ENVIRONMENT

Stephen M. Lorusso, P. N. Bompastore, M.T. Fertsch
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引用次数: 2

Abstract

This paper presents our findings on inserting the CrossCheckl test technology into Raytheon's CMOS, sub-micron, sea-of-gates COMPTest gate-array product family. Crosscheck's proprietary technology coupied with our integrated CAD software environment provided extremely high test coverage accommodating complex fault models. Our evaluation of scan versus Crosscheck demonstrated that Crosscheck is a superior testmethodology. Fewer constraints were imposed on the design, a substantial reduction in tester vectors resulted, and high stuck-at NO fault coverage (>99%) was attained with relative ease. Introduction Integrated circuit complexities have risen at an exponential rate over the past decade. System requirements such as tight area constraints and substantial inter-chip signal propagation delays necessitate that more functionality be resident on a single integrated circuit. Large designs which were once 2-5 thousand gates in size are now over 100 thousand gates in size. Some projections indicate the number of gates per chip will approach 2 million by 1995. The performance requirements of integrated circuits have also been rapidly accelerating. ASIC designers today are presented with challenging projects which require the development of high speed (>50 MHz), high density ASICs in an ever shrinking design cycle window. The testability of these large, high performance circuits has become an increasing industry concern. The cost of testing these devices has become a major obstacle to their widespread use. Several surveys have been conducted to assess these cost factors. [l-41 Figure 1 illustrates a defect curve for integrated circuits. The defect level is defined as the percentage of devices which pass testing but actually contain physical defects. Crosscheck is a trademark of Crosscheck Technology, Inc. This parameter is a function of fault coverage and yield. As the graph shows, to keep the defect percentage below 0.1 percent it is necessary to achieve fault coverages in excess of 99%. With simple ad hoc fault detection techniques this has proven to be an extremely difficult achievement. As a result, structured design techniques, such as scan, have emerged in an attempt to facilitate the generation of tests which produce high fault coverage.
将交叉检查技术集成到雷神测试环境中
本文介绍了我们将CrossCheckl测试技术插入雷神公司的CMOS,亚微米,海门COMPTest门阵列产品系列的研究结果。Crosscheck的专有技术与我们集成的CAD软件环境相结合,提供了极高的测试覆盖率,可适应复杂的故障模型。我们对扫描与交叉检查的评估表明,交叉检查是一种优越的测试方法。在设计上施加更少的约束,导致测试向量的大幅减少,并且相对容易地获得高卡在NO故障覆盖率(>99%)。在过去的十年里,集成电路的复杂性以指数级的速度增长。系统要求,如严格的面积限制和大量的芯片间信号传播延迟,需要更多的功能驻留在单个集成电路上。曾经只有2-5千个门的大型设计现在已经超过了10万个门。一些预测表明,到1995年每个芯片的门数将接近200万个。对集成电路的性能要求也在迅速提高。ASIC设计人员今天面临着具有挑战性的项目,这些项目需要在不断缩小的设计周期窗口中开发高速(bbb50 MHz)、高密度ASIC。这些大型高性能电路的可测试性已成为业界日益关注的问题。测试这些设备的成本已经成为它们广泛使用的主要障碍。已经进行了几项调查来评估这些成本因素。图1显示了集成电路的缺陷曲线。缺陷级别定义为通过测试但实际上包含物理缺陷的设备的百分比。Crosscheck是Crosscheck Technology, Inc.的商标。该参数是故障覆盖率和产量的函数。如图所示,为了保持缺陷百分比低于0.1%,有必要实现超过99%的故障覆盖率。使用简单的临时故障检测技术,这已被证明是一项极其困难的成就。因此,结构化设计技术,如扫描,已经出现,以促进产生高故障覆盖率的测试的生成。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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