Floating Complementary JFET Differential Stage with Increased Rejection of input Common Mode Signal and Power-Supply Noises

Abstract

The circuit solutions that provide increase of common-mode rejection ratio (CMRR) and power-supply noises rejection ratio (PSRR) on a basic parameters of input "floating" complementary differential stage (FCDS) are proposed in the article. This subclass of differential stages is different by low noise level, high radiation hardness and ability of work at low temperatures through the use of junction field- effect transistors. The modified FCDS circuit simulating with CJFET transistors models, consider influence of cryogenic temperatures in LTspice simulation software results are showed. They show that CMRR and PSRR are improved by 2-3 orders of magnitude.