Latch-Up and Timing Failure Analysis of CMOS VLSI using Electron Beam Techniques

Abstract

An electron beam testing system has been established for CMOS failure analysis. Problems studied include leakage, latch-up, timing, short circuits, crystallographic defects and step coverage. Two applications are described in detail. Synchronous voltage contrast and EBIC imaging techniques have allowed latch-up paths in input protection diode structures and output drivers to be located. Voltage contrast waveform measurements have analysed timing spreads in ULAs; these have been shown to be related to the cell design and the layout.