On the Error Resiliency of Combinational Logic Cells - Implications for Nano-based Digital Design

Abstract

With continuous decrease of device geometries in the nanoscale era of digital design, increasing importance is given to the reliability aspect of basic building blocks. In this context, this brief discusses the inherent fault tolerance capability of conventional logic gates before proceeding with the analysis of error immune property of a subset of combinational standard cells present in commercial digital libraries. The analysis has led to the following inferences: (i) Compared to complex-gate implementation, discrete-gate based realization of compound logic functions enables a mean improvement in the error resiliency metric by 68.2%, and (ii) the associated increase in area overhead for discrete-gate realizations as a trade-off for enhanced fault tolerance over complex gate implementations is found to be 51.6% on average.