Optimizing GZIP compression accelerator for Zynq FPGAs

Abstract

In this paper we present the architecture and design optimizations brought to an FPGA GZIP compressor we previously designed. The initial design could reach a maximum throughput of 1.34 Gbps on a I'irtexb FPGA while the optimized implementation can reach up to 1.84 Gbps using a Zynq-7020 FPGA. The hardware compressor is up to 8x times faster than the software version running on an ARM CPU that has a clock frequency 6. 7x times higher.