An efficient computerized error control transceiver system for DSRC applications

Abstract

The dedicated short range communication (DSRC) is a spring-up technique that pushes intelligent transportation systems (ITS) into our habitual life. Intelligent transportation services involves safer and more coordinated way of using transport networks. Routine broadcast of vehicular safety messages is one of the perspectives of intelligent transportation systems. Developed countries such as Japan, USA and Europe customarily adopts FM0 and Manchester codes for DSRC in intelligent transportation systems to reach DC balance. Nonetheless, the coding diversity between the two codes restraints a fully reused VLSI architecture for the two coding methods. To unbound the limitation, the paper proposes similarity oriented logic simplification (SOLS) technique. The pressing feature of this technique is that it augments the hardware utilization rate (HUR) from 57.14% to 100% for the two encoding methods. The proposed architecture can fully support the DSRC standards of the developed countries. To enhance the efficiency of DSRC applications, the paper also proposes error detection and error correction through hamming codes. Hamming codes are used for error control. This paper ensures an error-free DSRC communication system along with area and power efficient encoder design. The paper is simulated in ModelSim 6.3f using VHDL. The design is implemented in Spartan 6 XC6SLX16.