The role of ion implantation in CMOS scaling: A tutorial review

Abstract

The structure of this review frames the discussion over three time periods; (1) the 4 decades since the mid-1970’s with the introduction and growth of Si-based ICs, first as bipolar and then MOS devices, focusing on the MOS scaling models developed by Robert Dennard at IBM, (2) a brief look at scaling issues for bulk planar CMOS in the late 2000’s, as limits of gate length shrinks became major problems and (3) an examination of channel length and width scaling for fully-depleted CMOS in the last decade. This note concludes with a mention of the challenges to further scaling presented by line-edge roughness and quantum confinement for the industry-standard form of bulk finFETs.The structure of this review frames the discussion over three time periods; (1) the 4 decades since the mid-1970’s with the introduction and growth of Si-based ICs, first as bipolar and then MOS devices, focusing on the MOS scaling models developed by Robert Dennard at IBM, (2) a brief look at scaling issues for bulk planar CMOS in the late 2000’s, as limits of gate length shrinks became major problems and (3) an examination of channel length and width scaling for fully-depleted CMOS in the last decade. This note concludes with a mention of the challenges to further scaling presented by line-edge roughness and quantum confinement for the industry-standard form of bulk finFETs.