Counterflow pipeline based dynamic instruction scheduling

Abstract

This paper proposes a new dynamic instruction scheduler called the Asynchronous Fast Dispatch Stack (AFDS). This approach utilizes asynchronous design techniques to implement a dispatch stack-based dynamic instruction issue mechanism. To maintain throughput and simplify dependency computations, the AFDS architecture includes a counterflow pipeline, which is modeled after the Counterflow Pipeline Processor (CFPP) proposed by Sproull and Sutherland (1994). The AFDS counterflow pipeline, however, propagates instruction dependency and completion information, rather than results and source operands. Preliminary results indicate that the AFDS is a promising application of the CFPP architecture.