{"title":"A wireless readout front-end device for portable EEG acquisition system","authors":"Yi-Chung Chen, Zong-Han Hsieh, W. Fang","doi":"10.1109/ISCE.2013.6570196","DOIUrl":null,"url":null,"abstract":"In this paper, the 32-channel readout front-end device with a Bluetooth 2.0 module and a MSP430 ultra-low power microcontroller for portable Electroencephalograph (EEG) acquisition is presented. In addition to the consideration of low power, low noise, and high efficient chip area usage, the extendable readout front-end chip is presented with a design of chopper-stabilized differential difference amplifier (CHDDA) for high common mode rejection ratio (CMRR) and the 10-bit successive approximation register analog-to-digital converter (SAR-ADC) for high Signal-to-Noise Ratio (SNR). The power consumption of each readout chip is about 80.268 μW, and the total system is about 134.6 mW under the power supply of ±1.8 V.","PeriodicalId":442380,"journal":{"name":"2013 IEEE International Symposium on Consumer Electronics (ISCE)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE International Symposium on Consumer Electronics (ISCE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCE.2013.6570196","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
In this paper, the 32-channel readout front-end device with a Bluetooth 2.0 module and a MSP430 ultra-low power microcontroller for portable Electroencephalograph (EEG) acquisition is presented. In addition to the consideration of low power, low noise, and high efficient chip area usage, the extendable readout front-end chip is presented with a design of chopper-stabilized differential difference amplifier (CHDDA) for high common mode rejection ratio (CMRR) and the 10-bit successive approximation register analog-to-digital converter (SAR-ADC) for high Signal-to-Noise Ratio (SNR). The power consumption of each readout chip is about 80.268 μW, and the total system is about 134.6 mW under the power supply of ±1.8 V.