K. Nii, M. Yabuuchi, H. Fujiwara, Y. Tsukamoto, Y. Ishii, T. Matsumura, Y. Matsuda
{"title":"A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry","authors":"K. Nii, M. Yabuuchi, H. Fujiwara, Y. Tsukamoto, Y. Ishii, T. Matsumura, Y. Matsuda","doi":"10.1109/ISQED.2013.6523648","DOIUrl":null,"url":null,"abstract":"We propose an enhanced high-density 6T-SRAM bitcell with multi-Vt asymmetric halo implant dose MOSFET (AH-MOS) by introducing additional masks. Modified mask structure contributes to reduce the number of halo implant dose masks and achieves dense 0.37 μm2 6T-SRAM bitcell without any area overhead, shrinking to a half size of our previous work. 4-Mbit SRAM test chips are fabricated using 45-nm bulk CMOS technology. Combining with write assist circuitry, the Vmin is reduced by 50 mV and standby leakage by 53%.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Symposium on Quality Electronic Design (ISQED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2013.6523648","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
We propose an enhanced high-density 6T-SRAM bitcell with multi-Vt asymmetric halo implant dose MOSFET (AH-MOS) by introducing additional masks. Modified mask structure contributes to reduce the number of halo implant dose masks and achieves dense 0.37 μm2 6T-SRAM bitcell without any area overhead, shrinking to a half size of our previous work. 4-Mbit SRAM test chips are fabricated using 45-nm bulk CMOS technology. Combining with write assist circuitry, the Vmin is reduced by 50 mV and standby leakage by 53%.