Low energy e-beam proximity lithography (LEEPL)

Abstract

Low energy e-beam proximity lithography (LEEPL) is proposed for integrated circuit lithography for the minimum feature size less than 0.1 /spl mu/m. This e-beam lithography is similar to optical proximity lithography except that photons are replaced by low energy electrons. Our new concept is based on an e-beam of 2 kV instead of 10 kV which has been used in early 80s by IBM. The great advantage of a low energy e-beam is that one can use 0.5 /spl mu/m thick silicon membrane mask without an absorbing metal layer of high atomic number. This thickness is sufficiently thin enough to fabricate Si stencil mask with feature size less than O. 1 /spl mu/m. Further more it is sufficiently thick to conduct heat away to peripheral bulk to keep the mask temperature acceptably low and sufficiently strong enough to support a few cm square membrane area. To write VLSI pattern on this mask membrane does not requires OPC (optical proximity correction), PSM (phase shift mask feature) and PEC (proximity effect correction) as in the case of advanced photo masks. The residual mask distortion caused by both stress relief during the mask fabrication and the framing the mask can be corrected by a fine tuning deflector built in the e-beam column. For mask heating distortion due to the e-beam irradiation, we estimate maximum lateral distortion as 10 nm at the power input of 6 mW for 1 cmx1 cm mask area. This input power corresponds to 3 /spl mu/A of the beam current and it has a power of exposing 120 wafers of 12 inch diameter per hour at an exposure dose of 0.2 /spl mu/C/cm/sup 2/. This exposure dose corresponds to the resist sensitivity of 1 /spl mu/C/cm/sup 2/ at 10 kV, which is typical for this type of application.