A VLSI hardware implementation study of SVDD algorithm using analog Gaussian-cell array for on-chip learning

Abstract

A feasibility study of VLSI hardware implementation of support vector domain description (SVDD) has been done in this work. The on-chip learning operation of SVDD algorithm was implemented by an analog Gaussian-cell array. By using a compact analog Gaussian-generation circuit, the center, height and width of the generated Gaussian kernel function feature can be programmed. Based on this Gaussian-generation circuit, a fully parallel architecture is developed to implement the on-chip learning operation, which is carried out by the proposed method. In this manner, the learning operation autonomously proceeds without any clock-based iteration, and self-converges with a high speed. A proof-of-concept processor is designed for sixteen learning sample vectors. From the circuit simulation results, the entire learning operation is accomplished within 0.6 μs, and the domain of sample space is described by a reduced number of sample vectors. In addition, the various forms of domain description can be realized by tuning the kernel function feature dynamically.