High-frequency Test Structures For Wafer-level Reliability

Abstract

A series of unique self-stressing reliability test structures suitable for investigation of reliability concerns (hot carriers, electromigration, oxide breakdown) under realistic integrated circuit operating conditions are reported. These structures contain on-chip voltage-controlled oscillators. Using only DC signals, high-frequency (>lo0 MHz with nanosecond rise and fall times) wafer-level reliability characterizations are performed. This work describes these self-stressing structures with an example of a high-frequency, hot-carrier degradation performed at the wafer-level.