Implementation of Binary Neural Network with Low Temperature Polycrystalline Silicon TFT SRAM Array

Abstract

Integration of signal pre-processing functions with the thin-film transistor (TFT) sensor array on the same substrate would be able to reduce the required hardware resource and power consumption for the data movement and subsequent processing. In this work, a 64×64 static random-access memory (SRAM) array is designed based on the low temperature polycrystalline silicon (LTPS) TFT for implementation of binary neural network (BNN), which is then used for recognition task with the MNIST dataset. The simulation results prove that a combination of the binary-operated SRAM and the noise-tolerant BNN would be able to alleviate the influence of device performance fluctuation to pattern recognition accuracy.