Output Phase Assignment for Area and Power Optimization in Multi-level Multi-output Combinational Logic Circuits

Santanu Chaudhury, Santanu Chattopadhyay
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引用次数: 5

Abstract

In binary decision diagram (BDD) based realization of logic circuits, the area and power consumption is determined by the total number of nodes of the BDD and the expected switching activity of the nodes. A proper polarity selection of the subfunctions can not only reduce the number of BDD nodes, but also the switching. For a multi-output function, more the sharing between the subfunctions, more is the reduction in the number of BDD nodes so also the power. A genetic algorithm based output phase selection of the multi-output function (in BDD form) is proposed in this paper. This idea when applied to a number of benchmark circuits, it is found to reduce the number of nodes in the BDD and hence the area and power. A trade-off has also been done for combined area and power minimization, considering the node switching as the major candidate for power consumption. It has been found that the proposed method minimizes the area by about 3% and power by about 14%
多级多输出组合逻辑电路中面积和功率优化的输出相位分配
在基于二进制决策图(BDD)的逻辑电路实现中,面积和功耗由BDD的节点总数和节点的预期切换活动决定。适当选择子函数的极性不仅可以减少BDD节点的数量,还可以减少BDD的切换。对于多输出函数,子函数之间的共享越多,BDD节点的数量减少越多,功率也随之减少。提出了一种基于遗传算法的多输出函数(BDD形式)的输出相位选择方法。当将此想法应用于许多基准电路时,发现它可以减少BDD中的节点数量,从而减少面积和功耗。考虑到节点交换是功耗的主要候选,还对面积和功耗最小化进行了权衡。实验结果表明,该方法可使面积减小约3%,功率减小约14%
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