G. Thareja, S. Chopra, B. Adams, N. Patil, Y. Ta, P. Porshnev, Y. Kim, S. Moffatt, D. Loftis, R. Brennan, G. Goodman, I. Abdelrehim, K. Saraswat, Y. Nishi
{"title":"Ultra shallow junctions with high dopant activation and GeO2 interfacial layer for gate dielectric in germanium MOSFETs","authors":"G. Thareja, S. Chopra, B. Adams, N. Patil, Y. Ta, P. Porshnev, Y. Kim, S. Moffatt, D. Loftis, R. Brennan, G. Goodman, I. Abdelrehim, K. Saraswat, Y. Nishi","doi":"10.1109/DRC.2010.5551970","DOIUrl":null,"url":null,"abstract":"For the first time, ultra shallow junctions (x<inf>j</inf> < 10nm) are demonstrated using Plasma Immersion Ion Implantation for both n-type and p-type dopants in Ge. High electrical activation (>1×10<sup>20</sup> cm<sup>−3</sup>) is achieved for all dopant atoms (P/As/Sb/B) using Laser Thermal Processing. We also show ultrathin (0.6nm), high quality GeO<inf>2</inf> interfacial layer for gate dielectric, which provides substrate orientation independent D<inf>it</inf> and mobility enhancement for Ge high-k N/P MOSFETs.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"117 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"68th Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2010.5551970","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
For the first time, ultra shallow junctions (xj < 10nm) are demonstrated using Plasma Immersion Ion Implantation for both n-type and p-type dopants in Ge. High electrical activation (>1×1020 cm−3) is achieved for all dopant atoms (P/As/Sb/B) using Laser Thermal Processing. We also show ultrathin (0.6nm), high quality GeO2 interfacial layer for gate dielectric, which provides substrate orientation independent Dit and mobility enhancement for Ge high-k N/P MOSFETs.
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