Impact of Random Telegraph Signals on 6T high-density SRAM in 28nm UTBB FD-SOI

Abstract

This work investigates the impact of Random Telegraph Signal (RTS) noise on a 6 Transistors single P-well Static Random Access Memory (6T-SRAM) manufactured in 28nm Ultra-Thin Body and Buried Oxide Fully-Depleted Silicon-On-Insulator (UTBB FD-SOI) technology. A SPICE-level bias-and time-dependent RTS model peculiar to UTBB FD-SOI, which considers both front- and back-gate of the device as RTS sources, is presented. The Bit-Error-Rate is evaluated on silicon dies through the write-ability (WA) failure criterion and with a dedicated back-biasing strategy. Simulations evidence the role of RTS-induced dynamic variability with respect to process variability and show a good agreement with measurements.