{"title":"A 76 GHz oscillator by high-Q differential transmission line loaded with split ring resonator in 65-nm CMOS","authors":"Deyun Cai, Y. Shang, Hao Yu, Junyan Ren, K. Yeo","doi":"10.1109/SIRF.2013.6489449","DOIUrl":null,"url":null,"abstract":"A power and area efficient CMOS oscillator by high-Q metamaterial resonator is introduced in this paper for phase noise improvement. The resonator is based on the differential transmission-line (T-line) loaded with split ring resonator (SRR), which can enhance the EM energy coupling and further improve the Q. The proposed oscillator is implemented in 65-nm CMOS process, which consumes 2.7 mA and occupies a compact core area of 480 μm × 320 μm. At the oscillation frequency (76 GHz), the measured phase noise is -108.8 dBc/Hz at 10 MHz offset and the figure-of-merit (FOM) is -182.1 dBc/Hz, which is 4 dB better than that of the standing-wave oscillator implemented on the same chip.","PeriodicalId":286070,"journal":{"name":"2013 IEEE 13th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"60 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE 13th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIRF.2013.6489449","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A power and area efficient CMOS oscillator by high-Q metamaterial resonator is introduced in this paper for phase noise improvement. The resonator is based on the differential transmission-line (T-line) loaded with split ring resonator (SRR), which can enhance the EM energy coupling and further improve the Q. The proposed oscillator is implemented in 65-nm CMOS process, which consumes 2.7 mA and occupies a compact core area of 480 μm × 320 μm. At the oscillation frequency (76 GHz), the measured phase noise is -108.8 dBc/Hz at 10 MHz offset and the figure-of-merit (FOM) is -182.1 dBc/Hz, which is 4 dB better than that of the standing-wave oscillator implemented on the same chip.