MOSFET drain engineering for low-power applications

Abstract

The lightly doped drain (LDD) transistor structure has been used for several sub-micron process generations to improve hot carrier immunity for 5-volt applications. The principal challenge for LDD design is to optimize current-drive capability, thus improving circuit performance, while maintaining acceptable hot-carrier lifetime. The challenge for deep sub-micron devices remains the same, but some of the design constraints have changed. Reduction of the supply voltage V/sub dd/ inherently improves the hot-carrier lifetime, thus potentially allowing greater latitude in MOS device design. In this paper, the current-drive capability of MOSFETs with various drain structures is studied for 3.3-volt applications.