S. Babu, D. Moni, Paul John Padickala, J. Azariah, S. Rajesh
{"title":"Fabrication and Characterization of PLD Deposited Crystalline Zno as Channel and Amorphous Zno as Gate Dielectric of the Thin Film FET","authors":"S. Babu, D. Moni, Paul John Padickala, J. Azariah, S. Rajesh","doi":"10.1109/ICDCSYST.2018.8605144","DOIUrl":null,"url":null,"abstract":"The pulsed laser deposited crystalline and amorphous zinc oxide thin-films for field effect transistor (FET) were investigated. The deposited layers of channel and gate dielectric are formed with significant uniformity and better stoichiometry with PLD. The thin-film sample annealed at 400°C, becomes crystalline, which is used for the channel and the as-deposited amorphous sample used as a gate dielectric layer in MOSFET. The material compositional, structural and surface morphological studies were carried out using X-Ray Diffraction and Atomic Force Microscopy respectively. The complex impedance analysis of fabricated FET was analyzed between source to gate and source to drain. The Current – Voltage (I-V) transfer and output characteristics of fabricated FET was analyzed using National Instruments PXI-4100.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICDCSYST.2018.8605144","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
The pulsed laser deposited crystalline and amorphous zinc oxide thin-films for field effect transistor (FET) were investigated. The deposited layers of channel and gate dielectric are formed with significant uniformity and better stoichiometry with PLD. The thin-film sample annealed at 400°C, becomes crystalline, which is used for the channel and the as-deposited amorphous sample used as a gate dielectric layer in MOSFET. The material compositional, structural and surface morphological studies were carried out using X-Ray Diffraction and Atomic Force Microscopy respectively. The complex impedance analysis of fabricated FET was analyzed between source to gate and source to drain. The Current – Voltage (I-V) transfer and output characteristics of fabricated FET was analyzed using National Instruments PXI-4100.