Crosspoint Arithmetic Processor architecture for wafer scale integration

Abstract

The crosspoint (or crossbar) switch allows direct connection between arbitrary pairs of processors, minimizing the communication time overhead, but is considered impractical for large numbers of processors because the number of required connections is proportional to the square of the number of processors. However, crosspoint switches are very useful for small configurations (tens vs. hundreds of processors). In this paper, the authors explore the use of a crosspoint switch as the backbone of a general parallel arithmetic processor. This approach is appealing because it permits a compact, simple and easily producible chip set that could perform a variety of signal processing functions at high speed. The design can also provide the reconfigurability critical for improving the fault tolerance of the architecture. The basic configuration of the Crosspoint Arithmetic Processor (CAP) system consists of three principal components: a 32*32 crosspoint switch, an array of 32 computational nodes (CN), and a system controller.<>