Single-chip implementation of a 32-bit microcontroller for motor drive

Abstract

A single-chip 32-bit microcontroller was designed for a motor drive; the architecture and the implementation issues such as the clock distribution and the chip test results including the power dissipation are presented in this paper. The microcontroller includes the SPARC processor a FPU, a memory controller, an interrupt controller and peripheral devices in a single-chip. The microcontroller was optimized for vector controlled motor drives demanding high performance number crunching capabilities. The microcontroller chip was fabricated using a 0.8 /spl mu/m DLM N-well. CMOS technology. The chip contained about 562,000 transistors, the chip size was 12.8 mm/spl times/12.7 mm and the power consumption was 1.69 W at the supply voltage of 5 V and the clock frequency of 30 MHz.