Electrical characterization of through silicon via (TSV) for high-speed memory application

Abstract

In this paper, we study three types of the interconnection between die and die for system-in-package (SIP). The first is the two-dimensional system-in-package (2-D SIP) which is side-by-side dies with wire bonding interconnection. The second is the three-dimensional system-in-package (3-D SIP) which stacks up two dies with wire bonding interconnection and the third is 3-D SIP with TSV interconnection. The propagation delay, insertion loss and return loss results will be compared among these three types interconnection. TSV interconnection shows the best performance among the three types due to its shortest interconnection path between die to die. We also study electrical characteristics of different TSV structure, like TSV size, TSV height, TSV pitch and the number of TSV stacked. Based on the analysis results, we will provide the design guideline for designer reference.