Terminal Guidance Law Hardware In The Loop Simulation Against Maneuvering Targets Using FPGA Based Floating Point Approach

Abstract

Missile-target interception accuracy is mainly dependent on guidance algorithms implemented on the onboard computer. Nowadays advanced guidance algorithms are used to cope with the increasing target's capabilities. Augmented proportional navigation guidance (APN) is one of the best guidance laws and the most efficient against highly maneuvering targets. Missile guidance loop has a complicated structure that comprises multiple minor loops that require a synchronized data collection from several sensors. That multitasking should be handled carefully to avoid any unrequired delays. So, implementation of these algorithms on a high-speed processor is a must to satisfy these requirements and to increase the missile's probability to hit the designated target. Field programmable gate array (FPGA) processors are generally recommended due to their high speed, low power consumption, and concurrent architecture design. In this research, APN guidance algorithm is designed using VHDL floating point approach and implemented on FPGA. Hardware-in-the-Loop (HIL) simulation is used to verify the designed algorithm and evaluate the overall performance of the designed model. A VHDL verifier toolbox in MATLAB® Simulink™ is used to link the FPGA processor with the missile model to construct the FPGA in the loop (FIL) simulation scheme. Simulation results from the FIL model are compared with simulation through different scenarios to evaluate the VHDL designed guidance law performance against highly maneuvering target.