Improving test generation by use of majority gates

Abstract

Scan testing and scan compression have become key components for reducing test cost. We present a novel technique to increase automatic test pattern generation (ATPG) effectiveness by identifying and exploiting instances of increasingly common “majority gates”. Test generation is modified so that better decision are made and care bits can be reduced. Consequently, test coverage, pattern count and CPU time can be improved. The new method requires no hardware support, and can be applied to any ATPG system, although scan compression methods can benefit the most.