Dora María Ballesteros Larrotta, Diana Marcela Moreno Enciso, Andrés Gaona Barrera
{"title":"Compression of biomédical signals on FPGA by DWT and run-length","authors":"Dora María Ballesteros Larrotta, Diana Marcela Moreno Enciso, Andrés Gaona Barrera","doi":"10.1109/ANDESCON.2010.5633621","DOIUrl":null,"url":null,"abstract":"In real time compression algorithms, the mathematical used in the model must be easily modeled in hardware language. Most of the developments have been probed on Field Programmable Gate Arrays (FPGA) because it is fast and reliable. In this work, we present the architecture for biomédical compression based on Discrete Wavelet Transform (DWT) and run length encoding: bank of register, coefficients block, control unit, multiplier/adder, thresholding and encoding. The DWT is performed in one level with sym4, the coefficients are threshold by hard rule and encoding is by zero run length. The hardware resources correspond to 7% of the available in the Spartan3 of Xilinx; the simulation of each module was on ModelSim.","PeriodicalId":359559,"journal":{"name":"2010 IEEE ANDESCON","volume":"212 3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE ANDESCON","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ANDESCON.2010.5633621","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
In real time compression algorithms, the mathematical used in the model must be easily modeled in hardware language. Most of the developments have been probed on Field Programmable Gate Arrays (FPGA) because it is fast and reliable. In this work, we present the architecture for biomédical compression based on Discrete Wavelet Transform (DWT) and run length encoding: bank of register, coefficients block, control unit, multiplier/adder, thresholding and encoding. The DWT is performed in one level with sym4, the coefficients are threshold by hard rule and encoding is by zero run length. The hardware resources correspond to 7% of the available in the Spartan3 of Xilinx; the simulation of each module was on ModelSim.