{"title":"Micro-2010: lead performance microprocessor of the year 2010-myth or reality?","authors":"M. Khaira","doi":"10.1109/ICVD.1999.745141","DOIUrl":null,"url":null,"abstract":"Can you imagine working on a PC powered by a processor with 100 BIPS (Billion Instructions Per Sec) of performance? Is a processor with 1 Billion transistors a reality? This talk describes what the Micro-2010 will be like and identifies the challenges involved in its design. We expect all aspects of life to be impacted by Micro-2010. Applications like tele-presence, augmented reality, and reality animation indicate that such microprocessor performance will be a critical enabling technology. This talk makes an attempt to describe the characteristic features of the microprocessors of 2010, and identifies the challenges involved in their design and test. Micro-2010 will run at a frequency in excess of 4 gigaHertz. Getting to that level of performance while meeting the power budget (<100 Watts) and area budget (<$500 cost) will require breakthroughs in circuit design methodologies, CAD tools and technologies, and process technology. If current design methodology trends continue, designing Micro-2010 will require every single VLSI design engineer graduating after 2005 to be hired into the team designing it! This implies that major breakthroughs in design methodology, enabled by a new generation of CAD tools, is essential for these designs to become a reality. The semiconductor process in 2010 will have a minimum feature size less than 0.1 micron and the transistors a gate oxide of the thickness of less than the height of 10 layers of silicon dioxide molecules. These dimensions are smaller than the wavelength of visible light and will require major breakthroughs in process technology. Given the expected volume of shipment of Micro-2010, an errata like the FDIV cannot be tolerated without severe financial ramifications. Avoiding errata in a 1 Billion Transistor design is practically impossible. The talk will identify specific research directions in the areas of design and CAD tools to meet the challenges of design of the Micro-2010 and propose potential solutions.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"212 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICVD.1999.745141","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
Can you imagine working on a PC powered by a processor with 100 BIPS (Billion Instructions Per Sec) of performance? Is a processor with 1 Billion transistors a reality? This talk describes what the Micro-2010 will be like and identifies the challenges involved in its design. We expect all aspects of life to be impacted by Micro-2010. Applications like tele-presence, augmented reality, and reality animation indicate that such microprocessor performance will be a critical enabling technology. This talk makes an attempt to describe the characteristic features of the microprocessors of 2010, and identifies the challenges involved in their design and test. Micro-2010 will run at a frequency in excess of 4 gigaHertz. Getting to that level of performance while meeting the power budget (<100 Watts) and area budget (<$500 cost) will require breakthroughs in circuit design methodologies, CAD tools and technologies, and process technology. If current design methodology trends continue, designing Micro-2010 will require every single VLSI design engineer graduating after 2005 to be hired into the team designing it! This implies that major breakthroughs in design methodology, enabled by a new generation of CAD tools, is essential for these designs to become a reality. The semiconductor process in 2010 will have a minimum feature size less than 0.1 micron and the transistors a gate oxide of the thickness of less than the height of 10 layers of silicon dioxide molecules. These dimensions are smaller than the wavelength of visible light and will require major breakthroughs in process technology. Given the expected volume of shipment of Micro-2010, an errata like the FDIV cannot be tolerated without severe financial ramifications. Avoiding errata in a 1 Billion Transistor design is practically impossible. The talk will identify specific research directions in the areas of design and CAD tools to meet the challenges of design of the Micro-2010 and propose potential solutions.