Time-dependent Multiple Gate Voltage Reliability of Hybrid Ferroelectric Charge Trap Gate Stack (FEG) GaN HEMT for Power Device Applications

Abstract

This experimental study examines the time-dependent dielectric breakdown (TDDB) on a hybrid charge trap gate stack for the normally OFF operation of the Ferroelectric charge trap GaN High Electron Mobility Transistor (FEG-HEMT) at room temperature. The abrupt change in drain current shows the hard break down (HBD) of the charge trap gate stack. A hybrid charge trap gate stack provides the percolation path at the gate recess edge. Step gate stress has been used to figure out the breakdown voltage and device failure current which are found to be 20V and 2.14 μA/mm respectively. The fitted parameter β (Weibull distribution slope) has been analyzed for the multiple-gate stress voltage 17V, 18V, and 19V. Based on the power law, the lifetime prediction has been investigated for 63.2%, 10%, and 0.1% failure rates on fitting the data to gate voltage 13.5V, 13.1V, and 12.5V, respectively, by extrapolation up to 10 years.