Thermal-aware task mapping in 3D manycores targeting high performance applications

Abstract

With increasing the density of power consumption of chip transistors, thermal management is now a vital concern in CMP design. Higher temperature operation of electrical circuits has several side effects such as performance degradation, more power consumption which leads to higher cooling cost and reliability issues. Therefore, thermal management becomes an important aspect of design especially in embedded systems due to several limitations such as area, cooling, cost and energy consumption. Task mapping and scheduling is one of the popular techniques for thermal management. In this paper, we propose a design time application mapping which considers performance and power consumption of 3D integration of manycore platform based on electrical interconnection network. Experimental results show that the proposed task mapping mechanism improves the peak temperature of the chip about 22% and 14% (in average) in real world benchmark and synthetic applications, respectively.