Optimization of a-SiGe:H Thin Film Transistors with HfO2 as gate insulator by TCAD simulations

Abstract

This paper presents the study and improvement of main electrical parameters of a-SiGe:H Thin Film Transistors (TFTs) such as subthreshold slope, threshold voltage, ION/IOFF ratio and effective mobility, by using different techniques such as selecting the architecture with better performance, by applying a planarization method to gate electrode by lift-off process in order to reduce steps between drain/source electrodes and the active layer, by studying the effect of gate oxide thickness over the electrical parameters, and incorporating hafnium oxide (HfO2) as high k gate insulator. Simulated results show that the best architecture is the staggered bottom gate planarized with a gate oxide thickness of 10 nm for SiO2 or 50 nm for HfO2.