Superconducting Josephson Junction FET-based Cryogenic Voltage Sense Amplifier

Shamiul Alam, Md. Mazharul Islam, M. S. Hossain, A. Aziz
{"title":"Superconducting Josephson Junction FET-based Cryogenic Voltage Sense Amplifier","authors":"Shamiul Alam, Md. Mazharul Islam, M. S. Hossain, A. Aziz","doi":"10.1109/DRC55272.2022.9855654","DOIUrl":null,"url":null,"abstract":"Cryogenic (cryo) memory blocks are envisioned to be crucial components for - (i) scalable quantum computing systems with> 1000 qubits [1], and (ii) superconducting (SC) single flux quantum (SFQ) systems [2]. Decades of research has led to a whole host of cryo-memory variants (SC, non-SC, and hybrid), and more are being actively explored. Despite having such massive interest in the search for cryo-storage solutions, the design possibilities for compatible sense amplifiers (SA) remain largely unexplored. The existing approaches for cryogenic sensing are mostly agnostic to the unique properties of the memory array [3]–[5]. For example, the recently proposed SC and twistronic memories promise seamless compatibility with the cryogenic processors in terms of speed, power, and temperature range [4]–[7]. However, they rely on current-driven read operation, and necessitate voltage-based sensing. Therefore, a current-based cryo-SA [3] cannot be used for these emerging cryo-memory variants. In this work, we propose a voltage sense amplifier (VSA) for cryogenic memories utilizing the Josephson junction field effect transistor (JJFET) [8] as the primary component, and the heater cryotron (hTron) [4], [9] as an auxiliary entity. We exploit their coupled interactions to sense ultra-low (< 1 mV) voltage difference (customary for many cryo-memory technologies [4]–[7]) between the binary memory states (0/1) at/below 4 Kelvin temperature.","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 Device Research Conference (DRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC55272.2022.9855654","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9

Abstract

Cryogenic (cryo) memory blocks are envisioned to be crucial components for - (i) scalable quantum computing systems with> 1000 qubits [1], and (ii) superconducting (SC) single flux quantum (SFQ) systems [2]. Decades of research has led to a whole host of cryo-memory variants (SC, non-SC, and hybrid), and more are being actively explored. Despite having such massive interest in the search for cryo-storage solutions, the design possibilities for compatible sense amplifiers (SA) remain largely unexplored. The existing approaches for cryogenic sensing are mostly agnostic to the unique properties of the memory array [3]–[5]. For example, the recently proposed SC and twistronic memories promise seamless compatibility with the cryogenic processors in terms of speed, power, and temperature range [4]–[7]. However, they rely on current-driven read operation, and necessitate voltage-based sensing. Therefore, a current-based cryo-SA [3] cannot be used for these emerging cryo-memory variants. In this work, we propose a voltage sense amplifier (VSA) for cryogenic memories utilizing the Josephson junction field effect transistor (JJFET) [8] as the primary component, and the heater cryotron (hTron) [4], [9] as an auxiliary entity. We exploit their coupled interactions to sense ultra-low (< 1 mV) voltage difference (customary for many cryo-memory technologies [4]–[7]) between the binary memory states (0/1) at/below 4 Kelvin temperature.
基于超导约瑟夫森结场效应晶体管的低温电压检测放大器
低温(cryo)存储块被设想为以下关键组件:(i) > 1000量子位的可扩展量子计算系统[1],以及(ii)超导(SC)单通量量子(SFQ)系统[2]。几十年的研究已经导致了大量的低温记忆变体(SC,非SC和混合),更多的正在积极探索中。尽管对低温存储解决方案的研究有如此大的兴趣,但兼容感放大器(SA)的设计可能性在很大程度上仍未被探索。现有的低温传感方法大多不知道存储阵列的独特性质[3]-[5]。例如,最近提出的SC和双涡旋存储器承诺在速度,功率和温度范围方面与低温处理器无缝兼容[4]-[7]。然而,它们依赖于电流驱动的读取操作,并且需要基于电压的传感。因此,基于电流的cryo-SA[3]不能用于这些新出现的低温记忆变体。在这项工作中,我们提出了一种用于低温存储器的电压检测放大器(VSA),该放大器采用约瑟夫森结场效应晶体管(JJFET)[8]作为主要元件,加热低温管(hTron)[4],[9]作为辅助元件。我们利用它们的耦合相互作用来感知在4开尔文/以下温度下二进制存储状态(0/1)之间的超低(< 1 mV)电压差(许多低温存储技术的惯例[4]-[7])。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信