Interconnect Technologies for Terabit-per-Second Die-to-Die Interfaces

Abstract

Seamless package-level integration of multiple dies for high-performance computing and networking requires broadband dense die-to-die interconnect. Organic packaging substrates offer lower cost and lower loss interconnect, whereas silicon interposers offer higher density interconnect. In this work, a silicon interposer is fabricated in a relatively inexpensive 0.35 μm CMOS technology as an alternative to conventional organic or silicon interposer substrates. Flip-chip assembly technologies such as solder and gold-stud bumping are discussed. Measured eye diagrams at 16.4 Gb/s and bathtub curves at 20 Gb/s show the impact of assembly and bumping technology on the link performance. Considering signal integrity issues such as inter-symbol interference (ISI) and crosstalk, the maximum achievable aggregate bit rate is estimated for different interconnect lengths.