Development of 14nm Tri-layered (s-Si/s-SiGe/s-Si) Channel DG- NanoFET

Abstract

Strained silicon technology based DG- NanoFET is developed at 14nm gate having capability in order to sustain device feature below 22nm technology node. The newly designed double gate NanoFET developed here constitute of the s-Si and s-SiGe layered system which is directly placed in device channel but the thicknesses of each layers are varied to that in the previously designed 22nm channel length device, which result in mobility of charge carrier increased tri-layered region of narrow channel. This reduction in channel thickness is in line with the existing technology scaling and the device performance resulted in achieving augmented performance. Due to symmetric electrostatic coupling with two gates in the device ballistic transport is experienced by the majority charge carriers. The hetero layered channel DG-NanoFET developed on 14nm gate length also provided 53.5% improvement in drive current to that of 22nm channel length with acceptable leakage current.