A methodology to identify critical interconnects affected by electromigration

Abstract

Electromigration damage in interconnects is a well-known bottleneck of integrated circuits, as it is responsible for performance degradation, affecting parameters like delay, power and frequency. To guarantee a better performance for longer time, the chip designer needs to identify critical wires in the circuit layout and to alter it using techniques that retard the electromigration impact on the circuit. In this work, it is proposed a methodology to identify the critical lines due to the electromigration effect. This methodology is applied to evaluate the performance degradation of a ring oscillator.