Design of 120∶1 frequency divider for a 12.6 GHz phase-locked loop

Abstract

A 120:1 frequency divider in 65-nm CMOS process is proposed. As a critical part of a 12.6 GHz PLL, the divider circuit divides the 12.6 GHz signal by a factor of 120 to achieve a 105 MHz reference signal. The design includes an 8:1 analog common mode logic (CML) divider followed by a 15:1 digital frequency divider. The measurement results show that it achieves a low phase noise of -109 dBc/Hz at 1 MHz offset, and a wide locking range from 8.3 GHz to 13.9 GHz. The size of the fabricated divider is 0.3 × 0.1 mm2.