A Symbolic Cell Synthesizer for CMOS IC Design

Abstract

A symbolic cell synthesizer is presented. It accepts a net-list as input and generates a design-rule independent symbolic layout (stick diagram). The user can specify topological constraints on pin and transistor positions, the maximum lengths of poly and diffusion wires, and a preferred layer for each electrical node. Cells are synthesized according to optimization criteria that include not only geometric factors, such as cell area and wire length, but also electrical performance, namely capacitance to the substrate and contact and via minimization.