Delay and power model for current-mode signaling in deep submicron global interconnects

Abstract

In this paper, closed-form expressions of delay and power dissipation based on the effective lumped element resistance and capacitance approximation of distributed RC lines are presented. A new closed-form solution of delay under step input excitation is developed, exhibiting an accuracy that is within 5% for a wide range of parameters. The usefulness of this solution is that both resistive and capacitive load termination is accurately modeled for use in current mode signaling. A new power dissipation model for current-mode signaling is developed to understand the design tradeoffs between current and voltage sensing. Based on these formulations, a comparison between voltage-mode repeater insertion technique and current-mode signaling over long global deep submicron interconnects is presented.