E. Milovanovic, N. Stojanovic, I. Milovanovic, T. Tokic, M. Stojcev
{"title":"Optimizing AT/sup 2/ measure of hexagonal systolic arrays","authors":"E. Milovanovic, N. Stojanovic, I. Milovanovic, T. Tokic, M. Stojcev","doi":"10.1109/MIEL.2002.1003336","DOIUrl":null,"url":null,"abstract":"The major features of adopting systolic arrays (SA) for special purpose processing architectures are: simple and regular design, concurrency in communications, and balancing computation with the I/O. In this paper we synthesize a family of hexagonal arrays, SA(r), that implement matrix multiplication. We have observed that the execution time of a hexagonal array, which has a minimal number of processing elements (PE) for a given problem size, can be reduced if the number of PEs is increased. Since the execution time and the number of PEs are the two most important performance measures of the systolic array, we take their product AT/sup 2/, AT/sup 2/=/spl Omega//sub r/(n)T/sub exe//sup 2/, to compare the arrays from this family. With respect to this performance measure, the best array is obtained for r=[n/2], where n is a dimension of square matrices while r indicates the extension, in terms of rows, of the array that has minimal number of processing elements for a given problem size.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MIEL.2002.1003336","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The major features of adopting systolic arrays (SA) for special purpose processing architectures are: simple and regular design, concurrency in communications, and balancing computation with the I/O. In this paper we synthesize a family of hexagonal arrays, SA(r), that implement matrix multiplication. We have observed that the execution time of a hexagonal array, which has a minimal number of processing elements (PE) for a given problem size, can be reduced if the number of PEs is increased. Since the execution time and the number of PEs are the two most important performance measures of the systolic array, we take their product AT/sup 2/, AT/sup 2/=/spl Omega//sub r/(n)T/sub exe//sup 2/, to compare the arrays from this family. With respect to this performance measure, the best array is obtained for r=[n/2], where n is a dimension of square matrices while r indicates the extension, in terms of rows, of the array that has minimal number of processing elements for a given problem size.