Fully-depleted accumulation-mode PMOSFET for 0.2 /spl mu/m SOI technology

Abstract

SOI technology is a promising candidate for low-voltage low-power applications where both partially and fully depleted devices can be used to fulfil the related requirements. One advantage of fully-depleted devices is that a single N+ gate process can be kept for an advanced CMOS process. We show in this paper that an accumulation-mode fully-depleted PMOSFET using an N+ gate can be optimized for a 0.2 /spl mu/m SOI CMOS technology.