A Layout Strategy for Reducing the Random Error of Analog Circuit Blocks

Abstract

Unavoidable process random variation causes mismatches to deviate the performance of many analog circuit blocks. In addition, the correlation between components is also related to the performance parameters of analog circuits. This paper proposes a layout strategy to reduce the random error by making the trade-offs among performance parameter, correlation coefficient, and area allocation cost. Simulation results also confirm the proposed area allocation strategy for typical analog circuit blocks.