Early failure model analysis and improvement of the upstream electromigration in 45nm Cu low-k interconnects

Abstract

The effect of early failure model on upstream EM reliability and its improvements are investigated in a 45nm CMOS process. The effective process optimizations of tapered via profile by organic under layer (ODL) over etch (OE) at chamfer area and enlarged trench CD have been analyzed and discussed. Recent observations shown tapered via profile at chamfer area can get much larger angle for barrier seed deposition and the trench CD enlargement can get larger deposition angle and larger process window for photo alignment process at the vertical section. With a better step coverage, the defect-free barrier seed layer will suppress via void formation and improve the upstream EM reliability.