W. Chien, Shunwang Chiang, S. Tseng, C.H.J. Huang, K. Yang, W. Wang, J. Zhou
{"title":"Practical WLRC methodology & applications in a wafer foundry","authors":"W. Chien, Shunwang Chiang, S. Tseng, C.H.J. Huang, K. Yang, W. Wang, J. Zhou","doi":"10.1109/RELPHY.2003.1197780","DOIUrl":null,"url":null,"abstract":"As the product life cycle shrinks, qualification needs to be completed in a much shorter time. This makes wafer level reliability (WLR) an important tool, enabling results to be obtained in a much shorter time. The two key issues for WLR are to guarantee the same failure mechanisms as conventional package-level reliability (PLR) and to maintain a statistically acceptable correlation (in terms of parameter estimation, lifetime projections and trend). We report the correlation of WLR and PLR tests and present WLR control (WLRC) methodology to ensure in-line reliability/process stability and to assist new technology development. We also present WLRC cases/plots/models, which show the benefits of a special control chart and principal component analysis (PCA). Apart from its use for in-line monitoring, by suitably designing the test structures and choosing the fail criteria, we also apply WLRC as a quick assessment of process/tool change qualification. WLRC can be embedded in the wafer acceptance test (WAT). We show how to use WLRC data to formulate reliability-WAT-yield models to facilitate yield improvement and reliability optimization.","PeriodicalId":344023,"journal":{"name":"2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual.","volume":"53 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RELPHY.2003.1197780","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
As the product life cycle shrinks, qualification needs to be completed in a much shorter time. This makes wafer level reliability (WLR) an important tool, enabling results to be obtained in a much shorter time. The two key issues for WLR are to guarantee the same failure mechanisms as conventional package-level reliability (PLR) and to maintain a statistically acceptable correlation (in terms of parameter estimation, lifetime projections and trend). We report the correlation of WLR and PLR tests and present WLR control (WLRC) methodology to ensure in-line reliability/process stability and to assist new technology development. We also present WLRC cases/plots/models, which show the benefits of a special control chart and principal component analysis (PCA). Apart from its use for in-line monitoring, by suitably designing the test structures and choosing the fail criteria, we also apply WLRC as a quick assessment of process/tool change qualification. WLRC can be embedded in the wafer acceptance test (WAT). We show how to use WLRC data to formulate reliability-WAT-yield models to facilitate yield improvement and reliability optimization.