Area and time co-optimization for system-on-a-chip based on consecutive testability

Abstract

This paper presents an area overhead and test time cooptimization method for SoCs based on consecutive testability. Consecutive testability of SoCs guarantees that we can handle any test sequence that requires consecutive application of test patterns at speed of system clock such as a test sequence for timing faults. The proposed method creates a test schedule and TAM using existing interconnects as much as possible. Moreover, the method allows tradeoff between area overhead and test time according to user defined ratio. Experimental results show that the proposed method can achieve lower area overhead compared to test bus architecture due to the utilization of existing interconnects as a part of TAM. keywords: system-on-a-chip, design for testability, test access mechanism, test scheduling, consecutive testability