A new fabrication method for self-aligned nanoscale I-MOS (impact-ionization MOS)

Abstract

I-MOS uses modulation of the avalanche breakdown voltage of a gated p-i-n structure to control the output current. Because the p-n junction barrier lowering is not the mechanism of current flow control in the device, it can reduce the subthreshold swing to less than 60 mV/dec at room temperature. However, there are two main obstacles to scale the I-MOS down to nanoscale regime: 1) the source and drain are made up of different types of dopants; 2) the i-region, which is not overlapped by the gate, lies between channel and source. Therefore, in the conventional I-MOS process, the gate, the source and the drain cannot be self-aligned. In this paper, a 130 nm n-channel I-MOS was fabricated for the first time using a novel self-aligned fabrication method. It showed normal transistor operation with dramatically small subthreshold swing (7.2 mV/dec) at room temperature. In addition, to make the I-MOS more practical, we also proposed a novel biasing scheme based on the device physics.