Warpage study of glob top cavity-up EPBGA packages

Abstract

This paper describes a warpage study on LSI Logic's cavity up 40/spl times/10 mm 503 EPBGA and 35/spl times/35 mm 313 EPBGA packages. The main objectives of this study are to evaluate the impacts of the major assembly process on the package warpage, and to determine the impact significance of die size, encapsulation size, encapsulation height and substrate thickness on the package warpage. The package construction and assembly processes are reviewed first. The packages are single tier, 4 layer laminate chip carriers with glob top encapsulation. The assembly processes include die attach, encapsulation, ball attach and marking. Full factorial experiments were designed with both 503 EPBGA and 313 EPBGA packages. Package warpages were measured after each major assembly process. The warpage mode was monitored, and the final package warpages after marking were used for experiment analysis. At LSI Logic, this study has been used to identify the variables to minimize warpage. This was possible without significant change to the overall package construction. LSI Logic is able to meet coplanarity requirement on the low cost 4 layer package structure.