R. Ciocoveanu, R. Weigel, A. Hagelauer, V. Issakov
{"title":"A Low Insertion-Loss 10–110 GHz Digitally Tunable SPST Switch in 22 nm FD-SOI CMOS","authors":"R. Ciocoveanu, R. Weigel, A. Hagelauer, V. Issakov","doi":"10.1109/BCICTS.2018.8550908","DOIUrl":null,"url":null,"abstract":"This paper presents a wideband digitally tunable SPST switch based on the travelling-wave concept that has been realized in a 22 nm FD-SOI CMOS technology. The digital control for return loss is performed through mutual inductance switching. Small-signal measurement results show that the proposed SPST switch achieves a bandwidth of 10–110 GHz, with an insertion loss of 1.2 dB at 60 GHz and a 24 dB isolation at 60 GHz, whereas large-signal measurements show a 1-dB compression point of +7 dBm at 24 GHz. Furthermore, the 3 digital control bits allow tuning return loss center frequency by approximately 7 GHz. The chip core size is $0.12\\ \\text{mm x}\\ 0.15\\ \\text{mm}$.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BCICTS.2018.8550908","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
This paper presents a wideband digitally tunable SPST switch based on the travelling-wave concept that has been realized in a 22 nm FD-SOI CMOS technology. The digital control for return loss is performed through mutual inductance switching. Small-signal measurement results show that the proposed SPST switch achieves a bandwidth of 10–110 GHz, with an insertion loss of 1.2 dB at 60 GHz and a 24 dB isolation at 60 GHz, whereas large-signal measurements show a 1-dB compression point of +7 dBm at 24 GHz. Furthermore, the 3 digital control bits allow tuning return loss center frequency by approximately 7 GHz. The chip core size is $0.12\ \text{mm x}\ 0.15\ \text{mm}$.