Fast, dense, predictable and 100% routable MACH 3 and 4 family

Abstract

This paper focuses on the silicon architecture of AMD's second generation Macro Array CMOS High Speed/High Density (MACH) family of PLDs. Implemented with an advanced 0.65 /spl mu/m technology and driven strongly by customer needs MACH 3 and 4 family is optimized for speed, predictability, density, flexibility and 100% routability. The major thrusts for the family are to allow the following: design changes without changing pinouts, 100% routability. Flexible PAL blocks, synchronous/asynchronous flexible macrocells with built-in XOR capability and up to 20 product terms of logic without any incremental delay, flexible set/reset and clocking control and 5 V in-circuit programmability with IEEE 1149.1 JTAG interface in 100-208 pins PQFP packages. MACH 3 and 4 family is designed to offer fixed, predictable worst-case pin-to-pin delays of 15 ns and external systems clock frequency up to 50+ MHz.<>