An extracting capacitance in a stacked DRAM cell by numerical method

Abstract

This paper reports a methodology and its application for extracting the capacitance of a stacked DRAM cell structure by a numerical technique. To calculate the cell and parasitic capacitance in a stacked DRAM cell, we employed the finite element method (FEM), and to generate a complicated three-dimensional mesh structure, we used a graphic user interface, a topography simulator and three dimensional grid generator. A concave cylindrical DRAM cell capacitor with a minimum feature size of 0.25 /spl mu/m was chosen as a test vehicle to check the validity of the simulation. In this work, 62 parasitic capacitance values with 4 cell capacitance values were extracted from a stacked DRAM cell structure.